The present invention relates to insulated gate bipolar transistors (IGBTs) and more specifically relates to a novel structure and process for making a punch-through type IGBT in float zone (non-epitaxial) silicon.
Present day IGBTs are commonly made as xe2x80x9cpunch-throughxe2x80x9d devices in which a D-MOS type structure is formed in the top of an epitaxially deposited silicon wafer. The epitaxially deposited layer is formed atop a higher concentration buffer layer of the same concentration type which is, in turn formed on a substrate of opposite concentration type and which acts as a minority carrier injection source. In such xe2x80x9cpunch-throughxe2x80x9d devices, the electric field across the silicon under reverse bias reaches from the top surface of the silicon to the buffer layer which acts as a depletion layer xe2x80x9cstopxe2x80x9d.
The N+ buffer layer in the punch-through type IGBT plays a key role in the operation of the device. Thus, the thickness and concentration of the N+ layer will greatly affect the switching and breakdown voltage characteristics of the device. As stated above, the buffer layer acts as a depletion layer stop when the device is under reverse bias, and the N+ buffer layer also has a low lifetime and controls the injection efficiency of one of the equivalent bipolar transistors forming the IGBT. When using the N+ buffer, a thinner Nxe2x88x92 epitaxial layer can be used, with a higher resistivity to achieve a particular breakdown requirement. As a general rule, and with a given technology, a punch-through type IGBT will have a lower forward voltage drop Vceon and a better switching trade off than a xe2x80x9cnon-punch-throughxe2x80x9d IGBT device.
The wafer used for a punch-through device is relatively thick, and can be easily processed by existing wafer implanters and other wafer fabrication equipment for high volume production without excessive breakage. However, wafers with epitaxially formed layers (xe2x80x9cepi wafersxe2x80x9d) are expensive. Thus, the conventional method of making a punch-through IGBT uses an epi wafer which is normally made by first growing an N+ layer on a boron doped substrate; followed by the epitaxial deposition of Nxe2x88x92 silicon on top of the N+ layer. The thickness and resistivity of the Nxe2x88x92 and N+ layers are easily adjustable to optimize the IGBT performance for low voltage but it is much harder to adjust or control the process for thicker and higher resistivity Nxe2x88x92 epitaxial silicon needed for higher voltage (in excess for example of about 600 volts) devices.
It is possible to form xe2x80x9cnon-punch-throughxe2x80x9d IGBT devices directly in a float zone (non-epi) material to reduce cost. Such devices, are described in an IEEE publication 0-7803-3106-0/96 entitled xe2x80x9cNPT-IGBT-Optimizing for Manufacturabilityxe2x80x9d by Darryl Burns et al. These devices employ a D-MOS junction pattern in the top of a float zone wafer which is thinned to a value dependant on a desired breakdown voltage and speed for the ultimate device and are then provided with a collector which is a relatively lightly doped shallow junction which is a relatively inefficient injector known as a xe2x80x9cweakxe2x80x9d or xe2x80x9ctransparentxe2x80x9d collector. (The terms collector and anode are frequently interchanged.) This technique produces a high speed device without the need for heavy metal or E beam lifetime killing.
The non-punch through device has no buffer layer and the electric field across the silicon does not reach the weak collector. Thus, these devices use less expensive float zone material, but do not work in the punch through mode.
The thickness of the non-punch-through IGBT wafer is determined by the device blocking voltage, which can range from about 80 microns for a 600 volt device to about 250 microns for a device which breaks down at 1700 volts. In general, the lower the breakdown voltage, the thinner the wafer must be. These ultra thin wafers experience excessive breakage during handling in the manufacturing process so that handling of the wafer must be kept to a minimum. Most production equipment used today for high volume production cannot handle these wafers without costly modification.
It is also known that a punch-through IGBT can be made in the less expensive float zone material. Thus, an N+ buffer layer can be added to the float zone device, as by implanting a high concentration buffer zone of well controlled gradient into the bottom surface of the wafer, in front of the weak anode. By creating a punch-through IGBT in a float zone wafer, one can reap the benefits of the lower wafer costs of the non-punch-through IGBT and the better Vceon and switching trade off of the punch through IGBT. The conventional way of creating the N+ buffer layer in the float zone material is by thinning the wafer to a precise thickness; implanting an N type dopant such as phosphorus or arsenic into the bottom surface of the silicon (after thinning); followed by a high temperature anneal (greater than about 600xc2x0 C.) to activate the dopant. A shallow P region is then formed on the bottom surface. However, there are several problems with this approach.
1. The float zone wafers are very thin (60 to 150 microns thick) and are subject to breakage during the implant and anneal steps.
2. When either phosphorus or antimony is used for the buffer layer N+ dopant, an implant energy of 600 KeV to 2 MeV is required to achieve the desired implant depth. Such high energy implanters are very expensive and take up a large space in wafer Fab facility.
3. To reduce wafer breakage, the N+ buffer layer can be formed prior to the backside metal deposition after the front side metallizing and patterning are done. However, with the front side metal already in place, the anneal of the N+ implant will be restricted to a temperature which is below the deposition temperature of the top side passivation layer which is 350xc2x0 C. to 425xc2x0 C. Therefore, only a very small portion of the implant dopant will be annealed, and the degree of annealing varies greatly over a very small temperature range.
In accordance with the invention a punch-through IGBT is formed in float zone, non-epi material by a novel process in which both a buffer layer and the collector are referred to the back surface of the wafer. After wafer thinning the N+ buffer layer is formed by an implant with hydrogen atoms in an energy range of 100 KeV to 500 KeV at a dose of 1E12 to 1E16 per cm2. This is followed by the formation of a weak anode, as by the implant of a shallow (about 0.1 micron to 0.5 micron) P type region, using, for example, boron atoms. The wafers are then annealed for 30 to 60 minutes at 300 to 400xc2x0 C. to activate the hydrogen implant, without damage to the structure (metals and passivation) on the top surface of the device. This is then followed by the deposition of a back contact, for example, Al/Ti/NiV/Ag on the backside.
Note that the anneal process can be integrated into the backside metal deposition process by heating the wafer in the sputtering tool under vacuum prior to the backside metal deposition.
Implanted hydrogen is known to behave as an N+ dopant after implant damage is annealed out. The typical annealing temperature is in the range of 250xc2x0 C. to 400xc2x0 C. and preferably between 350xc2x0 C. and 400xc2x0 C. It has been found that the activation of the implanted hydrogen is fairly stable and insensitive to temperature variation.
In accordance with a further feature of the present invention, the concentration gradient of the N+ buffer layer in a float zone IGBT with a weak anode is very accurately controlled by forming it with at least one hydrogen implant to a well controlled dose adjacent a weak collector. This implant can be a hydrogen implant at a dose of 1E12 to 1E16 atoms/cm2 and at an energy of 100 KeV to 500 KeV.
Multiple hydrogen implants of progressively shallower and progressively higher total dose can also be used to form a very well controlled maximum dose adjacent the weak collector. This will then even more accurately define the breakdown voltage, speed and Vce characteristics of the punch through non-epi wafer device.
In carrying out the above multiple implant feature of the invention any desired number of sequential implants can be used. Typically, three sequential implants can be made into the bottom of a thinned wafer of hydrogen at 1E13/cm2; 1E14/cm2 and 1E15/cm2 respectively, at energies of 200 KeV, 150 KeV and 100 KeV respectively. Other N type dopants can also be used. For example, sequential phosphorus implants can be made at 1E14/cm2 at 600 KeV and again at 450 KeV, respectively, although they display a greater sensitivity to the annealing condition.
After completing the novel hydrogen implant, the implant is annealed and a P collector implant is performed prior to deposition of the collector contact. The collector contact consists of sequential layers of aluminum, titanium, nickel vanadium and silver.
While the process of the invention is described for an IGBT, the invention can also be used in the manufacture of other devices, for example, power MOSFETs. Thus, the invention can be used to provide an improved ohmic contact on the backside of a wafer by implanting hydrogen, in the range of 5 to 100 KeV and dose of 1E15 atoms/cm2 to 1E16 atoms/cm2 into the backside of the Nxe2x88x92 wafer. The wafer is then annealed for 30 to 60 minutes at 300 to 400xc2x0 C., followed by the sputtering of a contact of layers of Ti/NiV/Ag on the N+ implanted backside of the wafer.